Transistors such as metal oxide semiconductor field effect transistors (MOSFETs) or simply field effect transistors (FETs) are the core building blocks of the vast majority of semiconductor integrated circuits. A FET includes source and drain regions between which a current can flow through a channel under the influence of a bias applied to a gate electrode that overlies the channel. Some integrated circuits, such as high performance microprocessors, can include millions of FETs. For such integrated circuits, decreasing transistor size and thus increasing transistor density has traditionally been a high priority in the semiconductor manufacturing industry. Transistor performance, however, must be maintained even as the transistor size decreases.
A FinFET is a type of transistor that lends itself to the dual goals of reducing transistor size while maintaining transistor performance. The FinFET is a three dimensional transistor formed in a thin fin structure that extends upwardly from a semiconductor substrate. Transistor performance, often measured by its transconductance, is proportional to the width of the transistor channel. In a FinFET the transistor channel is formed along and between the vertical sidewalls of the fin structure, so a wide channel, and hence high performance, can be achieved without substantially increasing the area of the substrate surface required by the transistor.
One important challenge with the implementation of FinFETs at reduced technology nodes is the improper doping of channel regions in the fin structures. Conventional processes dope fin structures at their surfaces and require annealing to diffuse dopants to desired locations deeper in the fin structures. During such processes, channel regions are encapsulated by overlying gate structures and surrounding source/drain regions and are doped by directing dopant ions through the adjacent source/drain regions. Therefore, desired doping of channel regions is difficult to attain. Further, while source/drain regions are doped directly through their surfaces, the thermal anneal processes required to move the dopants to desired locations often result in unwanted movement of source/drain dopants into channel regions.
Accordingly, it is desirable to provide integrated circuits and methods for fabricating integrated circuits having FinFETs with improved doped channel regions. In addition, it is desirable to provide methods for fabricating integrated circuits that implant dopants directly into channel regions through exposed channel region surfaces. Also, it is desirable to provide integrated circuits and methods for fabricating integrated circuits that form uniformly doped channel regions. Furthermore, other desirable features and characteristics will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.